The present device relates generally to electronic systems and, more particularly, to electronic systems and components exhibiting non-analogous reset strategies.
To contain and potentially shorten the design and development cycle time for large-scale systems, previously designed components, or modules, are commonly used. Such modules, having been designed for systems having differing reset requirements, often have differing clock and timing constraints. Some modules, for example, employ an asynchronous reset scheme, a synchronous reset scheme or a mix of both. Others employ a positive-edge-triggered clocking scheme, a negative-edge-triggered clocking scheme, a level sensitive scheme, a multi-phased scheme, and so on. In like manner, the convention used for resetting each module may differ. For each module, the reset strategy employed introduces timing constraints relative to the particular clocking scheme employed. Examples of such timing constraints include: a synchronous reset must arrive at the module for a specified duration before the active edge of the clock and/or be held at its active state for a specified duration after the clock edge; an asynchronous reset should not be released in close proximity to a change of clock state in a level sensitive clocking design; a reset signal should not be asserted, or de-asserted, in close proximity to an assertion or desertion of a set signal; the release of a reset signal is advantageously effected about simultaneously for all modules; and so on. From a systems viewpoint, the varying reset and clocking strategies produce a combinatorial complex set of design constraints.
To accommodate the varying clocking strategies among modules, conventional systems include a module-clock-generator that generates the various clocking signals, at appropriate frequency and phase relative to each other for proper system operation. Accommodation of the varying reset strategies is commonly somewhat less structured. Typically, because of the combinatorial nature of the problem, specific reset circuitry is designed for each modules, or for each set of modules having a similar combination of reset and clock configurations. While the design of each reset circuit may not be unduly burdensome, the system level design task of properly defining, configuring, and testing each of these circuits can be significant.
The use of specific, time-dependent, reset circuits also minimizes the likelihood that systems designed with such circuits with xe2x80x9cscalexe2x80x9d as technologies change, or as other features are added to the system. Similarly, the use of such a system as a future module in a larger system will only serve to exacerbate the problems associated with modules having differing reset strategies and timing constraints.
The present invention makes possible a reset circuit that is modular, scaleable, straightforward to implement, allows for simple and safe physical design implementation, and addresses problems stated in the Background hereinabove. The present invention is exemplified in a number of implementations and applications, some of which are summarized below.
According to an example embodiment of the present invention, a reset circuit is adapted to reset a plurality of circuit modules in a manner that addresses problems including those discussed in the Background hereinabove. The reset circuit includes a reset module adapted to generate a reset signal, a clock module and a plurality of synchronization modules. The clock module has an external clock reference and at least one clock module output for each of the plurality of circuit modules. A reset clock signal is provided to each of the circuit modules via the clock module outputs in response to the generated reset signal. The frequency of the clock module is selectable to an external clock reference. Each synchronization module is coupled to one of the plurality of circuit modules and has a reset input port coupled to the reset module and a clock input port coupled to one of the clock module outputs. The synchronization modules are adapted to synchronize the reset signal to the reset clock signal and to provide the synchronized reset signal to reset each circuit module. The circuit modules are adapted to enable internal resets in response to a reset signal.
In another example embodiment of the present invention, a plurality of circuit modules adapted to enable internal resets in response to a reset signal are reset using a method that addresses problems including those discussed in the Background hereinabove. A reset signal is generated, and a reset clock signal having a frequency of an external clock reference is sent to each circuit module in response to the generated reset signal. The reset signal is synchronized to the reset clock signal for each circuit module, and the synchronized reset signal is to reset each circuit module. When the reset is disabled, each circuit module releases its internal reset almost simultaneously.
The above summary is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and detailed description that follow more particularly exemplify these embodiments.